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Often, when looking at digital system signal plots over time there are these graphs with two parallel lines that often "swap" place. I am wondering what precisely they represent? I noticed they usually are used for busses, but for the rest I'm clueless. It's probably quite trivial This is an example of the graphs I mean, in this case from a discussion about how CPU's execute instructions:
Thanks in advance, Joshua |
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The parallel lines indicate a multi-bit bus, and represent any possible combinations of low/high values. This bus could be two bits, or 64 bits, or whatever the design calls for. As shown here, the grey regions indicate that the data value is unknown or indeterminate. In this case, immediately after the positive clock transition, the address and data are unknown. Soon, after that, the address data becomes stable and known. Some time after that the data is known and can be read. edit: As Peter says, the grey regions can also mean "don't care". |
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Since most logic and microprocessor IC's use edge clocked timing, it's when the transitions from 0-1 and 1-0 occur that are important to timing. The high and low parallel lines simply tell you that a line may be high or low but not some indeterminate level such as tri-state). In your case shown, greyed out means not valid data/address (multiple signals), not greyed out means they will be 0 or 1 but the data is valid. For example in the image you show When the clock goes 0-1, the program memory address's are being setup after the greyed (invalid address on the lines) time period. Once the address is stable (non-greyed) the data lines represent (but can be 0 or 1) valid and stable data until the access time passes. Then the data bus will contain either 0 or 1 as appropriate for the memory address. |
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The two parallel lines indicate times when the data on the bus is stable, and the crossovers indicate when the data may change. The shaded sections are times we don't know or care what value is on the bus. |
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