Some of you may be familiar with my blog posts on “A View from the Top: A Virtual Prototyping Blog”. Those blog posts covered virtual prototyping. As of beginning of this year, I have however shifted my responsibilities to FPGA-based prototyping or physical prototyping. So I felt that it would make sense to pass on the torch of “A View from the Top” to my colleagues Pat Sheridan and Malte Doerper who are now leading the way for virtual prototyping.

To write down my thoughts related to physical prototyping, I started a new blog under the name “Hitting the Mark”. Why “Hitting the Mark”? Well it points to my name: “De Schutter” which is Dutch for “Marksman”. “Hitting the Mark” also refers to the value that FPGA-based prototyping brings by enabling earlier software development, hardware verification and hardware-software validation, thus enabling companies to achieve their target product requirements or thus hitting the mark for the product.

In the coming months, I plan to update you on things that drew my attention, look into trends related to physical prototyping and offer colleagues in the industry a forum to give their view on the value of FPGA-based prototyping.

I hope you will enjoy reading these blog posts.

Best practices in FPGA-based prototyping from experts at NVIDIA, Intel, Synopsys, SanDisk and Cisco.

FPGA-based prototyping has been a key prototyping technique for many years. The steady increase in software content and thus the need to verify and validate the SoC in context of the software has resulted in an equally steady increase in its usage. FPGA-based prototyping or physical prototyping, as it is also called, offers a great way to develop software, verify the hardware in context of that software and validate the combined system in context of real-world interaction.

The growth in SoC and software complexity has called for integrated physical prototyping solutions in which the prototyping software and the FPGA system are co-developed to minimize prototype bring-up time, maximize performance and optimize debug capabilities.

On March 30, five FPGA-based prototyping users will share their experience with the methodology and provide best practices to maximize its value.

• Ramanan Sanjeevi Krishnan and Sivarama Prasad Valluri from NVIDIA will share the techniques they used to partition a complex SoC. The session touches upon the challenges seen in design partitioning and in handling the huge interconnects running between different FPGAs.
• Nathan Henderson from Intel will explain how he improved debug turnaround time in high speed designs. He will cover his experience with the fastest Real Time Debug (RTD) capabilities with the highest sampling rates, to the highest multi-FPGA synchronized probe capacity with external DDR3 RAM.
• Antonio Salazar from the IP team in Synopsys will discuss the use of FPGA prototypes to prototype interface IP. Antonio will show how designers can connect a FPGA system to multiple IP prototyping kits (eDDR4 with DDR4, MIPI CSI-2, HDMI 2.0 TX) to first prototype the standard interfaces and then develop a complete SoC prototype.
• Xin Zhao from SanDisk will describe how to address time-to-market by prototyping and validating a SoC design using physical prototypes. This presentation showcases how to architect a high-level plan to prototype an entire SoC on a FPGA system and implement various interfaces on a SSD controller along with some of the challenges faced.
• Jayanth Mekkoth and Subhra Bandyopadhyay from Cisco will share how to reduce the overall turnaround time and how to increase system performance using FPGA prototypes. Jayanth and Subhra will the use of templates to achieve a successful prototype, that includes guidelines for specifying an initial system, using an abstract flow, constraining the design, and analyzing results as well as back annotating timing to arrive at the overall system frequency.

In general, it is pretty rare to be able to meet with prototyping experts from such a wide variety of companies and industries within one day.

I hope to see you all there!

More information on the FPGA-based prototyping sessions at SNUG Silicon Valley 2016 is available here. To register for SNUG, click here.