How do some microcontrollers implement baud rates even though it uses crystal frequency not scalable to standard baud rates?

UART doesn't care as long as it is reasonably exact.

\$\frac{15000000}{230400}\approx65\$

\$65\cdot230400=14976000\$

So your UART is going to be too fast by a factor of \$\frac{15000}{14976}\approx1,002204\$. It becomes a problem at \$1+\frac{1}{2\cdot11}\approx1,045\$, when the time shift across 11 bits is more than half a bit.

Here is the 'big print' features description of a relatively high end ARM MCU.

There are a number of PLLs and dividers with prescalers and postscalers that are capable of creating almost any frequency you might need as an integer ratio. The PLL multiplies its input frequency by some integer, and a divider can divide by some number (not necessarily powers of 2 in each case).

Internal relatively high frequencies (around half a GHz in this case) are not a problem (as they would be if off the chip)- relatively little power is consumed.

The days of division only by powers of 2 ended quite some time ago, and now that PLLs are commonly applied we don't need to worry about the exact crystal frequency nearly as much. On the other hand we may need many different clock frequencies for multiple internal bus clocks, USB, Ethernet, UART etc. peripherals.

If you want to learn more about how these work, you can study some of the dedicated clock synthesis chips which are relatively simple (though still complex enough that some makers supply software to calculate the setup constants).

Modern SoCs use so-called PLL to generate (almost) any clock that might be needed for interfaces. In simplified terms, the PLL circuit employs a high-frequency VCO (Voltage-controlled oscillator), then uses difital frequency dividers on both VCO and input clock, and generates a voltage feedback based on the frequency ratio. This feedback controls the VCO, such that the entire loop is locked to the desired frequency.

This can be achieved using a modulator.

See for example the MSP430x1xx user guide. On page 260 it says:

The USART baud rate generator is capable of producing standard baud rates from non-standard source frequencies. The baud rate generator uses one prescaler/divider and a modulator as shown in Figure 13−7. This combination supports fractional divisors for baud rate generation.

_{(note the gray area)}

The division factor N is often a non-integer value of which the integer portion can be realized by the prescaler/divider. The second stage of the baud rate generator, the modulator, is used to meet the fractional part as closely as possible.

[...]

The BITCLK can be adjusted from bit to bit with the modulator to meet timing requirements when a non-integer divisor is needed. Timing of each bit is expanded by one BRCLK clock cycle if the modulator bit mi is set. Each time a bit is received or transmitted, the next bit in the modulation control register determines the timing for that bit. A set modulation bit increases the division factor by one while a cleared modulation bit maintains the division factor given by UxBR

[...]