MCST Elbrus-2C+

MCST Elbrus-2C+ (1891VM7YA / 1891ВМ7Я) CPU (2 Elbrus cores + 4 DSP cores ElCore-09), 500 MHz, 368 M transistors, 90 nm, 289 mm2. Power: 25W.

• L1 Instruction cache = 64 KB.
• 2 clusters in execution core.
• Register File: 256 registers (84 bits per register). Two Register Files (same data in each cluster).
• 6 ALUs (3 ALUs per cluster).
• L1 Data cache = 64 KB. 32 B/line. 4-WAY. Two copies (1 copy per cluster). 2 ports per copy. LRU (3 bits per 4 lines).
• L2 cache = 1 MB (per Elbrus core). ?-WAY, 64 B/line. There are 4 bits of tag for each 8-bytes word.

• L1 Data Cache Latency = 3 cycles for simple access via pointer
• L1 Data Cache Latency = 4 cycles for access with complex address calculation (size_t n, *p; n = p[n]).
• L2 Cache Latency = 9 cycles
• RAM Latency = 9 cycles + 94 ns for open RAM page
• RAM Latency = 9 cycles + 108 ns for random access

4 KB pages mode (64-bit system)

• Data TLB: 1024 items. Miss penalty = 16 cycles. The core can't make more than one TLB miss handling (Page walk) simultaneously.

  Size        Latency       Increase   Description

  64 K     3                           
 128 K     6               3           + 6 (L2)        
 256 K     8               2       
 512 K     9 +   4 ns      1 +  4 ns   
   1 M     9 +  24 ns          18 ns
   2 M     9 +  64 ns          30 ns   + 108 ns (RAM)
   4 M    11 +  92 ns      2 + 28 ns   
   8 M    17 + 104 ns      6 + 12 ns   + 16 (TLB miss, Page walk to L1)
  16 M    21 + 107 ns      4 +  3 ns   
  32 M    24 + 108 ns      3 +  1 ns   
  64 M    27 + 108 ns      3 +  0 ns   + 6 (Page walk to L2)
 128 M    29 + 118 ns      2 + 10 ns       
 256 M    31 + 139 ns      2 + 21 ns
 512 M    31 + 166 ns          27 ns   + 108 ns (Page walk to RAM)

• 8-bytes range cross penalty = 6 cycles
• 32-bytes range cross penalty = 10 cycles
• L1 B/W (Parallel Random Read with direct pointers) = 0.25 cycles per one access
• L1 B/W (Parallel Random Read with complex addresses) = 0.41 cycles per one access
• L2->L1 B/W (Parallel Random Read) = 1 cycles per L1 cache line (32 bytes) = 16 GB/s
• L2->L1 B/W (Read, 64 bytes step) = 1.5 cycles per L1 cache line (32 bytes)
• L2 Write (Write, 8 bytes step) = 0.5 cycles per write
• RAM Read B/W (Parallel Random Read) = 18 ns per L2 cache line (64 bytes) = 3500 MB/s
• RAM Read B/W (Read, 8 Bytes step) = 540 MB/s
• RAM Read B/W (Read, 64 Bytes step) = 3500 MB/s
• RAM Read B/W (Read, 8 Bytes step - pointer chasing) = 350 MB/s
• RAM Read B/W (Read, 64 Bytes step - pointer chasing) = 540 MB/s
• RAM Write B/W (Write, 8-64 Bytes step) = 3800 MB/s

MCST Elbrus-3S

MCST Elbrus-3S (1891VM5YA / 1891ВМ5Я) CPU, 500 MHz, 218M transistors, 90 nm, 9-metal layer, 142 mm2. Power: 13-20W.

MW3S1/C Module : 4 Elbrus-3S CPUs. Power: 120 W.

• L1 Data cache = 64 KB. 32 B/line. 4-WAY
• L1 Instruction cache = 64 KB.
• L2 cache = 2 MB. 9 cycles latency ?, 64 B/line
• Data TLB size = 1024 items.
• Instruction TLB size = 64 items.

Links

Elbrus-2C+ at Wikipedia

Elbrus-2C+ at MCST (Russian)